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<p>This typedef contains configuration information for the Video PHY core.  
 <a href="struct_x_hdmiphy1___config.html#details">More...</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a68b29fa4cdc4042e14e5d610e312c69e"><td class="memItemLeft" align="right" valign="top">u16&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___config.html#a68b29fa4cdc4042e14e5d610e312c69e">DeviceId</a></td></tr>
<tr class="memdesc:a68b29fa4cdc4042e14e5d610e312c69e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Device instance ID.  <a href="#a68b29fa4cdc4042e14e5d610e312c69e">More...</a><br/></td></tr>
<tr class="separator:a68b29fa4cdc4042e14e5d610e312c69e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2bbcc590627355bad185ca417e839a6e"><td class="memItemLeft" align="right" valign="top">UINTPTR&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___config.html#a2bbcc590627355bad185ca417e839a6e">BaseAddr</a></td></tr>
<tr class="memdesc:a2bbcc590627355bad185ca417e839a6e"><td class="mdescLeft">&#160;</td><td class="mdescRight">The base address of the core instance.  <a href="#a2bbcc590627355bad185ca417e839a6e">More...</a><br/></td></tr>
<tr class="separator:a2bbcc590627355bad185ca417e839a6e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad890da2c40e7f26bdc43fcb09473a327"><td class="memItemLeft" align="right" valign="top">XHdmiphy1_GtType&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___config.html#ad890da2c40e7f26bdc43fcb09473a327">XcvrType</a></td></tr>
<tr class="memdesc:ad890da2c40e7f26bdc43fcb09473a327"><td class="mdescLeft">&#160;</td><td class="mdescRight">HDMIPHY Transceiver Type.  <a href="#ad890da2c40e7f26bdc43fcb09473a327">More...</a><br/></td></tr>
<tr class="separator:ad890da2c40e7f26bdc43fcb09473a327"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abed1d8f66f62de3bf785f81d0acbfd63"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___config.html#abed1d8f66f62de3bf785f81d0acbfd63">TxChannels</a></td></tr>
<tr class="memdesc:abed1d8f66f62de3bf785f81d0acbfd63"><td class="mdescLeft">&#160;</td><td class="mdescRight">No.  <a href="#abed1d8f66f62de3bf785f81d0acbfd63">More...</a><br/></td></tr>
<tr class="separator:abed1d8f66f62de3bf785f81d0acbfd63"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af477236d1bfcdcf060a5d2bb64e46d8f"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___config.html#af477236d1bfcdcf060a5d2bb64e46d8f">RxChannels</a></td></tr>
<tr class="memdesc:af477236d1bfcdcf060a5d2bb64e46d8f"><td class="mdescLeft">&#160;</td><td class="mdescRight">No.  <a href="#af477236d1bfcdcf060a5d2bb64e46d8f">More...</a><br/></td></tr>
<tr class="separator:af477236d1bfcdcf060a5d2bb64e46d8f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9daac9ee0c1db4441707eb89d83e69f7"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__xhdmiphy1.html#ga3f9002a6b4bc8e47f9c1fa68f8d0fb15">XHdmiphy1_ProtocolType</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___config.html#a9daac9ee0c1db4441707eb89d83e69f7">TxProtocol</a></td></tr>
<tr class="memdesc:a9daac9ee0c1db4441707eb89d83e69f7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Protocol which TX is used for.  <a href="#a9daac9ee0c1db4441707eb89d83e69f7">More...</a><br/></td></tr>
<tr class="separator:a9daac9ee0c1db4441707eb89d83e69f7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac740909a82f7887fbb3b27bf25aeb99d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__xhdmiphy1.html#ga3f9002a6b4bc8e47f9c1fa68f8d0fb15">XHdmiphy1_ProtocolType</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___config.html#ac740909a82f7887fbb3b27bf25aeb99d">RxProtocol</a></td></tr>
<tr class="memdesc:ac740909a82f7887fbb3b27bf25aeb99d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Protocol which RX is used for.  <a href="#ac740909a82f7887fbb3b27bf25aeb99d">More...</a><br/></td></tr>
<tr class="separator:ac740909a82f7887fbb3b27bf25aeb99d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acad30878325a5832d62b791c22a2091a"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__xhdmiphy1.html#gaec55cf3dfcfa0c7cf9749c63690dd019">XHdmiphy1_PllRefClkSelType</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___config.html#acad30878325a5832d62b791c22a2091a">TxRefClkSel</a></td></tr>
<tr class="memdesc:acad30878325a5832d62b791c22a2091a"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX REFCLK selection.  <a href="#acad30878325a5832d62b791c22a2091a">More...</a><br/></td></tr>
<tr class="separator:acad30878325a5832d62b791c22a2091a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa5b946a35a56f444442b88bfa49ae1bc"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__xhdmiphy1.html#gaec55cf3dfcfa0c7cf9749c63690dd019">XHdmiphy1_PllRefClkSelType</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___config.html#aa5b946a35a56f444442b88bfa49ae1bc">RxRefClkSel</a></td></tr>
<tr class="memdesc:aa5b946a35a56f444442b88bfa49ae1bc"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX REFCLK selection.  <a href="#aa5b946a35a56f444442b88bfa49ae1bc">More...</a><br/></td></tr>
<tr class="separator:aa5b946a35a56f444442b88bfa49ae1bc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a41f3855163277fe3afeea97a489e1fd4"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__xhdmiphy1.html#gaec55cf3dfcfa0c7cf9749c63690dd019">XHdmiphy1_PllRefClkSelType</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___config.html#a41f3855163277fe3afeea97a489e1fd4">TxFrlRefClkSel</a></td></tr>
<tr class="memdesc:a41f3855163277fe3afeea97a489e1fd4"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX FRL REFCLK selection.  <a href="#a41f3855163277fe3afeea97a489e1fd4">More...</a><br/></td></tr>
<tr class="separator:a41f3855163277fe3afeea97a489e1fd4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad7df81b4c90d8f4d6ca34a614e7987d2"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__xhdmiphy1.html#gaec55cf3dfcfa0c7cf9749c63690dd019">XHdmiphy1_PllRefClkSelType</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___config.html#ad7df81b4c90d8f4d6ca34a614e7987d2">RxFrlRefClkSel</a></td></tr>
<tr class="memdesc:ad7df81b4c90d8f4d6ca34a614e7987d2"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX FRL REFCLK selection.  <a href="#ad7df81b4c90d8f4d6ca34a614e7987d2">More...</a><br/></td></tr>
<tr class="separator:ad7df81b4c90d8f4d6ca34a614e7987d2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2e9741628b8a5bb24c2f11e478f44b61"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__xhdmiphy1.html#ga4d998790546ec3dde5119376868686e6">XHdmiphy1_SysClkDataSelType</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___config.html#a2e9741628b8a5bb24c2f11e478f44b61">TxSysPllClkSel</a></td></tr>
<tr class="memdesc:a2e9741628b8a5bb24c2f11e478f44b61"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX SYSCLK selection.  <a href="#a2e9741628b8a5bb24c2f11e478f44b61">More...</a><br/></td></tr>
<tr class="separator:a2e9741628b8a5bb24c2f11e478f44b61"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aea6c3ccda8a54e9bdaac1730162e4200"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__xhdmiphy1.html#ga4d998790546ec3dde5119376868686e6">XHdmiphy1_SysClkDataSelType</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___config.html#aea6c3ccda8a54e9bdaac1730162e4200">RxSysPllClkSel</a></td></tr>
<tr class="memdesc:aea6c3ccda8a54e9bdaac1730162e4200"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX SYSCLK selectino.  <a href="#aea6c3ccda8a54e9bdaac1730162e4200">More...</a><br/></td></tr>
<tr class="separator:aea6c3ccda8a54e9bdaac1730162e4200"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac28bbc6cb3c52b7dfc77813be0af0be5"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___config.html#ac28bbc6cb3c52b7dfc77813be0af0be5">DruIsPresent</a></td></tr>
<tr class="memdesc:ac28bbc6cb3c52b7dfc77813be0af0be5"><td class="mdescLeft">&#160;</td><td class="mdescRight">A data recovery unit (DRU) exists in the design .  <a href="#ac28bbc6cb3c52b7dfc77813be0af0be5">More...</a><br/></td></tr>
<tr class="separator:ac28bbc6cb3c52b7dfc77813be0af0be5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2fb109c75352439b0e91bc457b98c110"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__xhdmiphy1.html#gaec55cf3dfcfa0c7cf9749c63690dd019">XHdmiphy1_PllRefClkSelType</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___config.html#a2fb109c75352439b0e91bc457b98c110">DruRefClkSel</a></td></tr>
<tr class="memdesc:a2fb109c75352439b0e91bc457b98c110"><td class="mdescLeft">&#160;</td><td class="mdescRight">DRU REFCLK selection.  <a href="#a2fb109c75352439b0e91bc457b98c110">More...</a><br/></td></tr>
<tr class="separator:a2fb109c75352439b0e91bc457b98c110"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae1e3334ec7a5182a8bfef0d88503c8b4"><td class="memItemLeft" align="right" valign="top">XVidC_PixelsPerClock&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___config.html#ae1e3334ec7a5182a8bfef0d88503c8b4">Ppc</a></td></tr>
<tr class="memdesc:ae1e3334ec7a5182a8bfef0d88503c8b4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of input pixels per clock.  <a href="#ae1e3334ec7a5182a8bfef0d88503c8b4">More...</a><br/></td></tr>
<tr class="separator:ae1e3334ec7a5182a8bfef0d88503c8b4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a82e81634c7d587692e6e3f9b39089651"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___config.html#a82e81634c7d587692e6e3f9b39089651">TxBufferBypass</a></td></tr>
<tr class="memdesc:a82e81634c7d587692e6e3f9b39089651"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX Buffer Bypass is enabled in the design.  <a href="#a82e81634c7d587692e6e3f9b39089651">More...</a><br/></td></tr>
<tr class="separator:a82e81634c7d587692e6e3f9b39089651"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a24b90de973754a4fb94bfea69b94f34c"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___config.html#a24b90de973754a4fb94bfea69b94f34c">HdmiFastSwitch</a></td></tr>
<tr class="memdesc:a24b90de973754a4fb94bfea69b94f34c"><td class="mdescLeft">&#160;</td><td class="mdescRight">HDMI fast switching is enabled in the design.  <a href="#a24b90de973754a4fb94bfea69b94f34c">More...</a><br/></td></tr>
<tr class="separator:a24b90de973754a4fb94bfea69b94f34c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad065247f3924daf6806ef1cd334ba877"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___config.html#ad065247f3924daf6806ef1cd334ba877">TransceiverWidth</a></td></tr>
<tr class="memdesc:ad065247f3924daf6806ef1cd334ba877"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transceiver Width seeting in the design.  <a href="#ad065247f3924daf6806ef1cd334ba877">More...</a><br/></td></tr>
<tr class="separator:ad065247f3924daf6806ef1cd334ba877"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adcca9b60afa4ab17f6ed5e9b02d33d19"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___config.html#adcca9b60afa4ab17f6ed5e9b02d33d19">ErrIrq</a></td></tr>
<tr class="memdesc:adcca9b60afa4ab17f6ed5e9b02d33d19"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error IRQ is enalbed in design.  <a href="#adcca9b60afa4ab17f6ed5e9b02d33d19">More...</a><br/></td></tr>
<tr class="separator:adcca9b60afa4ab17f6ed5e9b02d33d19"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a58fa36d2bb19fa3f64cc1dd65ae1aa54"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___config.html#a58fa36d2bb19fa3f64cc1dd65ae1aa54">AxiLiteClkFreq</a></td></tr>
<tr class="memdesc:a58fa36d2bb19fa3f64cc1dd65ae1aa54"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXI Lite Clock Frequency in Hz.  <a href="#a58fa36d2bb19fa3f64cc1dd65ae1aa54">More...</a><br/></td></tr>
<tr class="separator:a58fa36d2bb19fa3f64cc1dd65ae1aa54"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5baa13346e9d06864c9c1881bbbe621a"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___config.html#a5baa13346e9d06864c9c1881bbbe621a">DrpClkFreq</a></td></tr>
<tr class="memdesc:a5baa13346e9d06864c9c1881bbbe621a"><td class="mdescLeft">&#160;</td><td class="mdescRight">DRP Clock Frequency in Hz.  <a href="#a5baa13346e9d06864c9c1881bbbe621a">More...</a><br/></td></tr>
<tr class="separator:a5baa13346e9d06864c9c1881bbbe621a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab8a671320487b659cd238148c8c2895f"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___config.html#ab8a671320487b659cd238148c8c2895f">UseGtAsTxTmdsClk</a></td></tr>
<tr class="memdesc:ab8a671320487b659cd238148c8c2895f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Use 4th GT channel as TX TMDS clock.  <a href="#ab8a671320487b659cd238148c8c2895f">More...</a><br/></td></tr>
<tr class="separator:ab8a671320487b659cd238148c8c2895f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0096c127b7722fe2dcb4d385e65f8d45"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___config.html#a0096c127b7722fe2dcb4d385e65f8d45">RxMaxRate</a></td></tr>
<tr class="memdesc:a0096c127b7722fe2dcb4d385e65f8d45"><td class="mdescLeft">&#160;</td><td class="mdescRight">Max rate of RX.  <a href="#a0096c127b7722fe2dcb4d385e65f8d45">More...</a><br/></td></tr>
<tr class="separator:a0096c127b7722fe2dcb4d385e65f8d45"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acb9c68daaac54dbc6f206f129bac144f"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___config.html#acb9c68daaac54dbc6f206f129bac144f">TxMaxRate</a></td></tr>
<tr class="memdesc:acb9c68daaac54dbc6f206f129bac144f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Max rate of TX.  <a href="#acb9c68daaac54dbc6f206f129bac144f">More...</a><br/></td></tr>
<tr class="separator:acb9c68daaac54dbc6f206f129bac144f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4dc8998eda218c14bd49e0ed7c374657"><td class="memItemLeft" align="right" valign="top">XHdmiphy1_ClkPrimitive&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___config.html#a4dc8998eda218c14bd49e0ed7c374657">TxClkPrimitive</a></td></tr>
<tr class="memdesc:a4dc8998eda218c14bd49e0ed7c374657"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX Clock Primitive.  <a href="#a4dc8998eda218c14bd49e0ed7c374657">More...</a><br/></td></tr>
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<tr class="memdesc:a20e2ef2834674875c1643c822897ad42"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX Clock Primitive.  <a href="#a20e2ef2834674875c1643c822897ad42">More...</a><br/></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>This typedef contains configuration information for the Video PHY core. </p>
</div><h2 class="groupheader">Field Documentation</h2>
<a class="anchor" id="a58fa36d2bb19fa3f64cc1dd65ae1aa54"></a>
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<p>AXI Lite Clock Frequency in Hz. </p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#gaa15dd35a9b1670aab091738d3ecca9df">XHdmiphy1_Hdmi_CfgInitialize()</a>, <a class="el" href="xhdmiphy1__hdmi__intr_8c.html#a80cae1429b5d37ffec8de9763de00f56">XHdmiphy1_HdmiRxClkDetFreqChangeHandler()</a>, and <a class="el" href="xhdmiphy1__hdmi__intr_8c.html#afc3e2c76a28022e9d12a96990cc2fc83">XHdmiphy1_HdmiTxClkDetFreqChangeHandler()</a>.</p>

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<p>The base address of the core instance. </p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#gac17db2af38544c85cb299d147fcdac16">XHdmiphy1_CfgInitialize()</a>, <a class="el" href="group__xhdmiphy1.html#gaa113dd9ce96c346ef9b757947eb340fe">XHdmiphy1_ClkDetAccuracyRange()</a>, <a class="el" href="group__xhdmiphy1.html#gafaece55136a95db26cf37edcd53c96f8">XHdmiphy1_ClkDetCheckFreqZero()</a>, <a class="el" href="group__xhdmiphy1.html#gab2369998b0e4635bced93881e51cc8fe">XHdmiphy1_ClkDetEnable()</a>, <a class="el" href="group__xhdmiphy1.html#gac39e0926826a1e127514c8350ddcde21">XHdmiphy1_ClkDetFreqReset()</a>, <a class="el" href="group__xhdmiphy1.html#gabb75647ab6dfd99febccba18593e86d8">XHdmiphy1_ClkDetGetRefClkFreqHz()</a>, <a class="el" href="group__xhdmiphy1.html#ga5a055146c6b3aa1da1991a0041dc11f7">XHdmiphy1_ClkDetSetFreqLockThreshold()</a>, <a class="el" href="group__xhdmiphy1.html#ga46cb7e8a6cc10a61bbfb7126f85e8cec">XHdmiphy1_ClkDetSetFreqTimeout()</a>, <a class="el" href="group__xhdmiphy1.html#gac2f877b2581399c3344d1555d05df2df">XHdmiphy1_ClkDetTimerClear()</a>, <a class="el" href="group__xhdmiphy1.html#gacbffa1bd1304f2f69a32aa1a22573052">XHdmiphy1_ClkDetTimerLoad()</a>, <a class="el" href="group__xhdmiphy1.html#gab511031505e9679f2bd243d68eb725f4">XHdmiphy1_Clkout1OBufTdsEnable()</a>, <a class="el" href="group__xhdmiphy1.html#ga7b7a69d580eaac17960b977851aead25">XHdmiphy1_DruEnable()</a>, <a class="el" href="group__xhdmiphy1.html#gae2d190888890d12b1524b5d5065e5e57">XHdmiphy1_DruGetRefClkFreqHz()</a>, <a class="el" href="group__xhdmiphy1.html#gab5da59924fa5189f7141d950e6d31a50">XHdmiphy1_DruGetVersion()</a>, <a class="el" href="group__xhdmiphy1.html#ga5ccf265013fcb1e013775dc9a8563c87">XHdmiphy1_DruReset()</a>, <a class="el" href="group__xhdmiphy1.html#ga02899710d93b44ffa5d6f87637d67809">XHdmiphy1_DruSetCenterFreqHz()</a>, <a class="el" href="group__xhdmiphy1.html#gaa91560e5b99db9d90042b548a76da7a6">XHdmiphy1_GetSysClkDataSel()</a>, <a class="el" href="group__xhdmiphy1.html#gabf0e7c8a542401ba275640fabee19940">XHdmiphy1_GetSysClkOutSel()</a>, <a class="el" href="group__xhdmiphy1.html#gaf6a4e05c5b6141f00bdfa2ae1f30b15a">XHdmiphy1_GetVersion()</a>, <a class="el" href="group__xhdmiphy1.html#gaff834a7a15854c09af35144299a4f980">XHdmiphy1_GtUserRdyEnable()</a>, <a class="el" href="group__xhdmiphy1.html#gaa15dd35a9b1670aab091738d3ecca9df">XHdmiphy1_Hdmi_CfgInitialize()</a>, <a class="el" href="group__xhdmiphy1.html#ga16dfea31e43d9da2c4c00cd0785b6248">XHdmiphy1_HdmiDebugInfo()</a>, <a class="el" href="group__xhdmiphy1.html#gae9070f7158ccb8538edf80a5ec4c8da6">XHdmiphy1_HdmiGtDruModeEnable()</a>, <a class="el" href="xhdmiphy1__hdmi__intr_8c.html#a0c603299dc1bafabcf0ecfe920bd412b">XHdmiphy1_HdmiGtRxResetDoneLockHandler()</a>, <a class="el" href="xhdmiphy1__hdmi__intr_8c.html#ad65db64a87467172db631b182c2ddd2d">XHdmiphy1_HdmiGtTxResetDoneLockHandler()</a>, <a class="el" href="xhdmiphy1__hdmi__intr_8c.html#a80cae1429b5d37ffec8de9763de00f56">XHdmiphy1_HdmiRxClkDetFreqChangeHandler()</a>, <a class="el" href="xhdmiphy1__hdmi__intr_8c.html#afc3e2c76a28022e9d12a96990cc2fc83">XHdmiphy1_HdmiTxClkDetFreqChangeHandler()</a>, <a class="el" href="group__xhdmiphy1.html#ga57aac6b723825d9999dc5419d067bda3">XHdmiphy1_IBufDsEnable()</a>, <a class="el" href="group__xhdmiphy1.html#gacb93fcb29ad3045d260d3fbbaa0be81e">XHdmiphy1_InterruptHandler()</a>, <a class="el" href="group__xhdmiphy1.html#gabb09df5f9b1e2f799160dd944d8ae935">XHdmiphy1_IntrDisable()</a>, <a class="el" href="group__xhdmiphy1.html#gaf1923a89392fcc152f571818d2ad564f">XHdmiphy1_IntrEnable()</a>, <a class="el" href="group__xhdmiphy1.html#gac05b90ab984e726f1ddde5cf265915d9">XHdmiphy1_IsPllLocked()</a>, <a class="el" href="group__xhdmiphy1.html#ga0b46b7c2c9c6d5fbe7e7c2a6d226b985">XHdmiphy1_MmcmLocked()</a>, <a class="el" href="group__xhdmiphy1.html#ga6d652ca1a4650bc5a2762d381a110f6b">XHdmiphy1_MmcmLockedMaskEnable()</a>, <a class="el" href="group__xhdmiphy1.html#ga13859cf616b98f6d37336128b9f3f21a">XHdmiphy1_MmcmPowerDown()</a>, <a class="el" href="group__xhdmiphy1.html#ga47707c2203c7788afdfb22fe1ae438db">XHdmiphy1_MmcmReset()</a>, <a class="el" href="group__xhdmiphy1.html#ga2b93ca125219d62f19817168267ddfc5">XHdmiphy1_MmcmSetClkinsel()</a>, <a class="el" href="group__xhdmiphy1.html#gafe6529e3429c7199f87f7f8fc7f43fe0">XHdmiphy1_PatgenEnable()</a>, <a class="el" href="group__xhdmiphy1.html#ga51d10d93fa76ebe0c031600b61955d4d">XHdmiphy1_PatgenSetRatio()</a>, <a class="el" href="group__xhdmiphy1.html#gaf1fbb7de9d26abab7332a62932be9d85">XHdmiphy1_PowerDownGtPll()</a>, <a class="el" href="group__xhdmiphy1.html#ga8dc19df05e15d413e62ff62d2c22c023">XHdmiphy1_RegisterDebug()</a>, <a class="el" href="group__xhdmiphy1.html#ga7f1f22be7f2029c396c015e322475790">XHdmiphy1_ResetGtPll()</a>, <a class="el" href="group__xhdmiphy1.html#ga117b1b06a6044a0574731e960e8e304a">XHdmiphy1_ResetGtTxRx()</a>, <a class="el" href="group__xhdmiphy1.html#ga08947cfedb541b7f95242c82ee60a8c5">XHdmiphy1_SelfTest()</a>, <a class="el" href="group__xhdmiphy1.html#gafb115f999643adac66932d6c4a44de1c">XHdmiphy1_SetBufgGtDiv()</a>, <a class="el" href="group__xhdmiphy1.html#ga615fe597062a12b286153f2ee8007e91">XHdmiphy1_SetPolarity()</a>, <a class="el" href="group__xhdmiphy1.html#ga041ec28c400f1b4cb662d9670e0feff3">XHdmiphy1_SetPrbsSel()</a>, <a class="el" href="group__xhdmiphy1.html#ga704b9c7161c4ac92beaa07113caaa36c">XHdmiphy1_SetRxLpm()</a>, <a class="el" href="group__xhdmiphy1.html#ga755a209f0abe848a3508017f83ad4c62">XHdmiphy1_SetTxPostCursor()</a>, <a class="el" href="group__xhdmiphy1.html#gad9dd0d271c9be7416e55adc535257cea">XHdmiphy1_SetTxPreEmphasis()</a>, <a class="el" href="group__xhdmiphy1.html#gaa01b2c0214336ba205fcac3c8fd7675d">XHdmiphy1_SetTxVoltageSwing()</a>, <a class="el" href="xhdmiphy1__hdmi_8c.html#a355efb9fbbf8e3d0102738e912971bca">XHdmiphy1_TxAlignReset()</a>, <a class="el" href="xhdmiphy1__hdmi_8c.html#a579cfbb41fbd51477dd902f9a1758826">XHdmiphy1_TxAlignStart()</a>, <a class="el" href="group__xhdmiphy1.html#gae474ac8f1f2997229ec25e7584a4b827">XHdmiphy1_TxPrbsForceError()</a>, and <a class="el" href="group__xhdmiphy1.html#ga0fa2836b8aac17e187bf1e01a462001a">XHdmiphy1_WriteCfgRefClkSelReg()</a>.</p>

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<p>Device instance ID. </p>

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          <td class="memname">u32 XHdmiphy1_Config::DrpClkFreq</td>
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<p>DRP Clock Frequency in Hz. </p>

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          <td class="memname">u8 XHdmiphy1_Config::DruIsPresent</td>
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<p>A data recovery unit (DRU) exists in the design . </p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#ga22de3338657208e2ee991d68f0248195">XHdmiphy1_GetRefClkSourcesCount()</a>, <a class="el" href="group__xhdmiphy1.html#gaa15dd35a9b1670aab091738d3ecca9df">XHdmiphy1_Hdmi_CfgInitialize()</a>, <a class="el" href="xhdmiphy1__hdmi_8c.html#aefc037877ed6316c6995845442a31971">XHdmiphy1_HdmiCpllParam()</a>, <a class="el" href="group__xhdmiphy1.html#ga16dfea31e43d9da2c4c00cd0785b6248">XHdmiphy1_HdmiDebugInfo()</a>, <a class="el" href="xhdmiphy1__hdmi_8c.html#a026bd874ba52e36d8f0e770b962543f9">XHdmiphy1_HdmiQpllParam()</a>, <a class="el" href="xhdmiphy1__hdmi__intr_8c.html#a80cae1429b5d37ffec8de9763de00f56">XHdmiphy1_HdmiRxClkDetFreqChangeHandler()</a>, and <a class="el" href="group__xhdmiphy1.html#ga57aac6b723825d9999dc5419d067bda3">XHdmiphy1_IBufDsEnable()</a>.</p>

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          <td class="memname"><a class="el" href="group__xhdmiphy1.html#gaec55cf3dfcfa0c7cf9749c63690dd019">XHdmiphy1_PllRefClkSelType</a> XHdmiphy1_Config::DruRefClkSel</td>
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<p>DRU REFCLK selection. </p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#gac17db2af38544c85cb299d147fcdac16">XHdmiphy1_CfgInitialize()</a>, <a class="el" href="group__xhdmiphy1.html#ga22de3338657208e2ee991d68f0248195">XHdmiphy1_GetRefClkSourcesCount()</a>, <a class="el" href="group__xhdmiphy1.html#ga5a0a82f90d7a0f1c4c8180cfb465de0a">XHdmiphy1_HdmiRxTimerTimeoutHandler()</a>, and <a class="el" href="group__xhdmiphy1.html#ga57aac6b723825d9999dc5419d067bda3">XHdmiphy1_IBufDsEnable()</a>.</p>

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          <td class="memname">u32 XHdmiphy1_Config::ErrIrq</td>
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<p>Error IRQ is enalbed in design. </p>

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          <td class="memname">u8 XHdmiphy1_Config::HdmiFastSwitch</td>
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<p>HDMI fast switching is enabled in the design. </p>

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<p>Number of input pixels per clock. </p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#ga2aa401218d0bc4c64c2210f85ccee457">XHdmiphy1_Hdmi21Config()</a>, and <a class="el" href="group__xhdmiphy1.html#ga69e679f0c4444350910817be69cde77c">XHdmiphy1_SetHdmiTxParam()</a>.</p>

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<p>No. </p>
<p>of active channels in RX </p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#ga70ecb3c5614ea8c97c0bc56bd395ac2c">XHdmiphy1_Ch2Ids()</a>, and <a class="el" href="group__xhdmiphy1.html#ga8dc19df05e15d413e62ff62d2c22c023">XHdmiphy1_RegisterDebug()</a>.</p>

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<p>RX Clock Primitive. </p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#gafa361514e8315c25876867a1ded2c99b">XHdmiphy1_HdmiCfgCalcMmcmParam()</a>, <a class="el" href="group__xhdmiphy1.html#ga16dfea31e43d9da2c4c00cd0785b6248">XHdmiphy1_HdmiDebugInfo()</a>, and <a class="el" href="group__xhdmiphy1.html#ga5dc7ec503e2e78570719440c12773984">XHdmiphy1_MmcmStart()</a>.</p>

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          <td class="memname"><a class="el" href="group__xhdmiphy1.html#gaec55cf3dfcfa0c7cf9749c63690dd019">XHdmiphy1_PllRefClkSelType</a> XHdmiphy1_Config::RxFrlRefClkSel</td>
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<p>RX FRL REFCLK selection. </p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#gac17db2af38544c85cb299d147fcdac16">XHdmiphy1_CfgInitialize()</a>, <a class="el" href="group__xhdmiphy1.html#gabb75647ab6dfd99febccba18593e86d8">XHdmiphy1_ClkDetGetRefClkFreqHz()</a>, <a class="el" href="group__xhdmiphy1.html#ga22de3338657208e2ee991d68f0248195">XHdmiphy1_GetRefClkSourcesCount()</a>, <a class="el" href="group__xhdmiphy1.html#ga2aa401218d0bc4c64c2210f85ccee457">XHdmiphy1_Hdmi21Config()</a>, <a class="el" href="xhdmiphy1__hdmi__intr_8c.html#a80cae1429b5d37ffec8de9763de00f56">XHdmiphy1_HdmiRxClkDetFreqChangeHandler()</a>, and <a class="el" href="group__xhdmiphy1.html#ga5a0a82f90d7a0f1c4c8180cfb465de0a">XHdmiphy1_HdmiRxTimerTimeoutHandler()</a>.</p>

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<p>Max rate of RX. </p>

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          <td class="memname"><a class="el" href="group__xhdmiphy1.html#ga3f9002a6b4bc8e47f9c1fa68f8d0fb15">XHdmiphy1_ProtocolType</a> XHdmiphy1_Config::RxProtocol</td>
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<p>Protocol which RX is used for. </p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#ga70ecb3c5614ea8c97c0bc56bd395ac2c">XHdmiphy1_Ch2Ids()</a>, <a class="el" href="group__xhdmiphy1.html#ga22de3338657208e2ee991d68f0248195">XHdmiphy1_GetRefClkSourcesCount()</a>, and <a class="el" href="group__xhdmiphy1.html#gab75f3892f884d01f855d607291eba269">XHdmiphy1_IsHDMI()</a>.</p>

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          <td class="memname"><a class="el" href="group__xhdmiphy1.html#gaec55cf3dfcfa0c7cf9749c63690dd019">XHdmiphy1_PllRefClkSelType</a> XHdmiphy1_Config::RxRefClkSel</td>
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<p>RX REFCLK selection. </p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#gac17db2af38544c85cb299d147fcdac16">XHdmiphy1_CfgInitialize()</a>, <a class="el" href="group__xhdmiphy1.html#gabb75647ab6dfd99febccba18593e86d8">XHdmiphy1_ClkDetGetRefClkFreqHz()</a>, <a class="el" href="group__xhdmiphy1.html#ga22de3338657208e2ee991d68f0248195">XHdmiphy1_GetRefClkSourcesCount()</a>, <a class="el" href="group__xhdmiphy1.html#ga1e17b8f3099b9edb96bdf732671b7efc">XHdmiphy1_Hdmi20Config()</a>, <a class="el" href="group__xhdmiphy1.html#ga2aa401218d0bc4c64c2210f85ccee457">XHdmiphy1_Hdmi21Config()</a>, <a class="el" href="xhdmiphy1__hdmi__intr_8c.html#a80cae1429b5d37ffec8de9763de00f56">XHdmiphy1_HdmiRxClkDetFreqChangeHandler()</a>, <a class="el" href="group__xhdmiphy1.html#ga5a0a82f90d7a0f1c4c8180cfb465de0a">XHdmiphy1_HdmiRxTimerTimeoutHandler()</a>, and <a class="el" href="group__xhdmiphy1.html#ga57aac6b723825d9999dc5419d067bda3">XHdmiphy1_IBufDsEnable()</a>.</p>

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          <td class="memname"><a class="el" href="group__xhdmiphy1.html#ga4d998790546ec3dde5119376868686e6">XHdmiphy1_SysClkDataSelType</a> XHdmiphy1_Config::RxSysPllClkSel</td>
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<p>RX SYSCLK selectino. </p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#gac17db2af38544c85cb299d147fcdac16">XHdmiphy1_CfgInitialize()</a>, <a class="el" href="group__xhdmiphy1.html#ga97e1d4070dafe5a73d9bf60621382c98">XHdmiphy1_GetPllType()</a>, and <a class="el" href="group__xhdmiphy1.html#ga1d8702f582054727e5bafc4e6cf32739">XHdmiphy1_HdmiUpdateClockSelection()</a>.</p>

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<p>Transceiver Width seeting in the design. </p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#gaa15dd35a9b1670aab091738d3ecca9df">XHdmiphy1_Hdmi_CfgInitialize()</a>, <a class="el" href="group__xhdmiphy1.html#gafa361514e8315c25876867a1ded2c99b">XHdmiphy1_HdmiCfgCalcMmcmParam()</a>, <a class="el" href="xhdmiphy1__hdmi_8c.html#aefc037877ed6316c6995845442a31971">XHdmiphy1_HdmiCpllParam()</a>, and <a class="el" href="xhdmiphy1__hdmi_8c.html#a026bd874ba52e36d8f0e770b962543f9">XHdmiphy1_HdmiQpllParam()</a>.</p>

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<p>TX Buffer Bypass is enabled in the design. </p>

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<p>No. </p>
<p>of active channels in TX </p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#ga70ecb3c5614ea8c97c0bc56bd395ac2c">XHdmiphy1_Ch2Ids()</a>, and <a class="el" href="group__xhdmiphy1.html#ga8dc19df05e15d413e62ff62d2c22c023">XHdmiphy1_RegisterDebug()</a>.</p>

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<p>TX Clock Primitive. </p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#gafa361514e8315c25876867a1ded2c99b">XHdmiphy1_HdmiCfgCalcMmcmParam()</a>, <a class="el" href="group__xhdmiphy1.html#ga16dfea31e43d9da2c4c00cd0785b6248">XHdmiphy1_HdmiDebugInfo()</a>, and <a class="el" href="group__xhdmiphy1.html#ga5dc7ec503e2e78570719440c12773984">XHdmiphy1_MmcmStart()</a>.</p>

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          <td class="memname"><a class="el" href="group__xhdmiphy1.html#gaec55cf3dfcfa0c7cf9749c63690dd019">XHdmiphy1_PllRefClkSelType</a> XHdmiphy1_Config::TxFrlRefClkSel</td>
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<p>TX FRL REFCLK selection. </p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#gac17db2af38544c85cb299d147fcdac16">XHdmiphy1_CfgInitialize()</a>, <a class="el" href="group__xhdmiphy1.html#gabb75647ab6dfd99febccba18593e86d8">XHdmiphy1_ClkDetGetRefClkFreqHz()</a>, <a class="el" href="group__xhdmiphy1.html#ga22de3338657208e2ee991d68f0248195">XHdmiphy1_GetRefClkSourcesCount()</a>, <a class="el" href="group__xhdmiphy1.html#ga2aa401218d0bc4c64c2210f85ccee457">XHdmiphy1_Hdmi21Config()</a>, and <a class="el" href="xhdmiphy1__hdmi__intr_8c.html#afc3e2c76a28022e9d12a96990cc2fc83">XHdmiphy1_HdmiTxClkDetFreqChangeHandler()</a>.</p>

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<p>Max rate of TX. </p>

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          <td class="memname"><a class="el" href="group__xhdmiphy1.html#ga3f9002a6b4bc8e47f9c1fa68f8d0fb15">XHdmiphy1_ProtocolType</a> XHdmiphy1_Config::TxProtocol</td>
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<p>Protocol which TX is used for. </p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#ga70ecb3c5614ea8c97c0bc56bd395ac2c">XHdmiphy1_Ch2Ids()</a>, <a class="el" href="group__xhdmiphy1.html#ga22de3338657208e2ee991d68f0248195">XHdmiphy1_GetRefClkSourcesCount()</a>, and <a class="el" href="group__xhdmiphy1.html#gab75f3892f884d01f855d607291eba269">XHdmiphy1_IsHDMI()</a>.</p>

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          <td class="memname"><a class="el" href="group__xhdmiphy1.html#gaec55cf3dfcfa0c7cf9749c63690dd019">XHdmiphy1_PllRefClkSelType</a> XHdmiphy1_Config::TxRefClkSel</td>
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<p>TX REFCLK selection. </p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#gac17db2af38544c85cb299d147fcdac16">XHdmiphy1_CfgInitialize()</a>, <a class="el" href="group__xhdmiphy1.html#gabb75647ab6dfd99febccba18593e86d8">XHdmiphy1_ClkDetGetRefClkFreqHz()</a>, <a class="el" href="group__xhdmiphy1.html#ga22de3338657208e2ee991d68f0248195">XHdmiphy1_GetRefClkSourcesCount()</a>, <a class="el" href="group__xhdmiphy1.html#ga1e17b8f3099b9edb96bdf732671b7efc">XHdmiphy1_Hdmi20Config()</a>, <a class="el" href="group__xhdmiphy1.html#ga2aa401218d0bc4c64c2210f85ccee457">XHdmiphy1_Hdmi21Config()</a>, <a class="el" href="xhdmiphy1__hdmi__intr_8c.html#afc3e2c76a28022e9d12a96990cc2fc83">XHdmiphy1_HdmiTxClkDetFreqChangeHandler()</a>, and <a class="el" href="group__xhdmiphy1.html#ga57aac6b723825d9999dc5419d067bda3">XHdmiphy1_IBufDsEnable()</a>.</p>

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          <td class="memname"><a class="el" href="group__xhdmiphy1.html#ga4d998790546ec3dde5119376868686e6">XHdmiphy1_SysClkDataSelType</a> XHdmiphy1_Config::TxSysPllClkSel</td>
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<p>TX SYSCLK selection. </p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#gac17db2af38544c85cb299d147fcdac16">XHdmiphy1_CfgInitialize()</a>, <a class="el" href="group__xhdmiphy1.html#ga97e1d4070dafe5a73d9bf60621382c98">XHdmiphy1_GetPllType()</a>, and <a class="el" href="group__xhdmiphy1.html#ga1d8702f582054727e5bafc4e6cf32739">XHdmiphy1_HdmiUpdateClockSelection()</a>.</p>

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          <td class="memname">u8 XHdmiphy1_Config::UseGtAsTxTmdsClk</td>
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<p>Use 4th GT channel as TX TMDS clock. </p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#ga70ecb3c5614ea8c97c0bc56bd395ac2c">XHdmiphy1_Ch2Ids()</a>, <a class="el" href="xhdmiphy1__hdmi__intr_8c.html#ad65db64a87467172db631b182c2ddd2d">XHdmiphy1_HdmiGtTxResetDoneLockHandler()</a>, and <a class="el" href="xhdmiphy1__hdmi__intr_8c.html#afc3e2c76a28022e9d12a96990cc2fc83">XHdmiphy1_HdmiTxClkDetFreqChangeHandler()</a>.</p>

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<p>HDMIPHY Transceiver Type. </p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#gac17db2af38544c85cb299d147fcdac16">XHdmiphy1_CfgInitialize()</a>, <a class="el" href="group__xhdmiphy1.html#ga70ecb3c5614ea8c97c0bc56bd395ac2c">XHdmiphy1_Ch2Ids()</a>, <a class="el" href="group__xhdmiphy1.html#gae2d190888890d12b1524b5d5065e5e57">XHdmiphy1_DruGetRefClkFreqHz()</a>, <a class="el" href="group__xhdmiphy1.html#gaa91560e5b99db9d90042b548a76da7a6">XHdmiphy1_GetSysClkDataSel()</a>, <a class="el" href="group__xhdmiphy1.html#gabf0e7c8a542401ba275640fabee19940">XHdmiphy1_GetSysClkOutSel()</a>, <a class="el" href="group__xhdmiphy1.html#gaa15dd35a9b1670aab091738d3ecca9df">XHdmiphy1_Hdmi_CfgInitialize()</a>, <a class="el" href="xhdmiphy1__hdmi__intr_8c.html#ad65db64a87467172db631b182c2ddd2d">XHdmiphy1_HdmiGtTxResetDoneLockHandler()</a>, <a class="el" href="group__xhdmiphy1.html#gada0844e8a6a828bb7d512259aca11498">XHdmiphy1_HdmiTxTimerTimeoutHandler()</a>, <a class="el" href="group__xhdmiphy1.html#ga8dc19df05e15d413e62ff62d2c22c023">XHdmiphy1_RegisterDebug()</a>, and <a class="el" href="group__xhdmiphy1.html#ga0fa2836b8aac17e187bf1e01a462001a">XHdmiphy1_WriteCfgRefClkSelReg()</a>.</p>

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